One challenge of fabricating, or etching, shallow trench isolation (STI) features in a substrate is microloading between regions of dense features and regions of isolated features. Microloading manifests itself as differences in feature profile and etch depth between regions of high feature density and regions of low feature density on a substrate in which the features are being etched. For example, regions of low feature density may etched to a depth that is different than an etch depth corresponding to the regions of high feature density.
As an example, the inventors have observed that, for certain devices, such as advanced node devices (e.g., sub 40 nm), there may be variation in critical dimension (CD) spacing of features from cell to cell which can result in STI depth variation corresponding to the varying CD. As another example, for Flash memory devices that require patterning at very small device nodes, there is a need to pattern with a self-aligned double patterning (SADP) processes due to litho limitations. However, the inventors have observed that, due to the SADP processes, there may be a variation in the CD spacing from feature to feature, which results in an alternating, bi-modal (or random) depth variation from feature to feature due to microloading. For DRAM devices the inventors have observed that there is also a microloading effect between storage node contact (SNC) and buried node contact (BNC) areas.
Thus, the inventors have provided improved methods for fabricating STI structures that may provide improved control over etch depth microloading.